1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices, and more particularly to flash-type electrically erasable programmable read only memory (EEPROM) devices with overerasure preventing structures.
2. Description of the Related Art
A nonvolatile semiconductor memory is a type of memory that retains stored data when a power source is removed. There are various types of nonvolatile semiconductor memories, such as read only memories (ROMs), programmable read only memories (PROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs).
EPROMs are erased by ultra-violet light, which in general takes a long time. However, flash EEPROMs are erased much more quickly, and thus are widely used in data processing systems requiring reprogrammable nonvolatile semiconductor memories.
Flash EEPROMs generally include an array of transistor memory cells, each having a floating gate and a control gate thereon. During erasure, as with EEPROMs, entire sets of memory cells of the flash EEPROM are erased. A flash EEPROM often includes a plurality of sectors (or blocks) into which the memory cell array is divided, and all memory cells in the selected sector are erased simultaneously. Once the flash EEPROM is bulk erased, selected memory cells are programmed.
To enhance capacity of memory cells and speed of the flash EEPROM, there have been developed technologies of memory cell arrays with NOR-type and NAND-type. In the NOR-type memory cell array, drains and sources of floating gate cell transistors are connected in parallel between neighboring bit (or drain) and source lines. In the NAND-type memory cell array, a plurality of series-connected floating gate cell transistors are connected between corresponding bit and source lines. However, even though the NAND-type memory cell array exhibits increased capacity of memory cells, it has a slower access speed, because of the small cell current, as compared to the NOR-type memory cell array (herein referred to as a NOR-type flash EEPROM). On the other hand, the NOR-type flash EEPROM exhibits advantages such as high speed and random access. The NOR-type flash EEPROM is disclosed in an article entitled "A Novel Dual String NOR (DuSNOR) Memory Cell Technology Scalable to the 256 Mbit and 1 Gbit Flash Memories", by K. S. Kim et al., IEDM 1995, pages 263-266.
A conventional NOR-type flash EEPROM is of a virtual ground type. FIG. 1 is a schematic plan view of a portion of a virtual ground type flash EEPROM memory cell array according to a prior art, and FIG. 2 is a cross-sectional view taken along a line 2-2' of FIG. 1. FIG. 3 is an equivalent circuit diagram of the memory cell array shown in FIG. 1.
Referring to FIGS. 1 and 2, heavily doped n.sup.+ diffusion regions 14, 16 and 18 are respectively buried beneath spaced apart and parallel ones of thick field oxide strips 12 on a p-type semiconductor substrate 10. A thin oxide (or dielectric) layer 20 is formed on a surface of substrate 10 between two neighboring field oxide strips 12. Floating gates 22 of polycrystalline silicon are formed on oxide layers 20. Floating gates 22 extend beyond oxide layers 20 so as to cover portions of field oxide strips 12. Insulating layers 24 are formed on floating gates 22. An elongate control gate layer 26 of conductive material, extending perpendicularly to field oxide strips 12, is formed on insulating layers 24. Seen also in FIG. 1, parallel elongated control gate layers 26 and 28 are word lines WL1 and WL2, respectively.
Returning to FIG. 2, an elongated diffusion region 16 is a common source line CSL, and the elongated diffusion regions 14 and 18 are bit lines BL1 and BL2, respectively. Channel regions 30 are disposed between two neighboring diffusion regions, underlying floating gates 22.
Referring also to FIG. 3, erase, program and read-out operations of memory cells are now described.
To erase all the shown memory cells M11.about.M22, a high voltage of about 12 V is applied to the common source line CSL, with the word lines WL1 and WL2 grounded and the bit lines BL1 and BL2 floated. Electrons are then transported from floating gates 22 to source regions, i.e. common source line CSL, by Fowler-Nordheim tunneling, thereby causing threshold voltages of memory cell transistors to become about 2 V. The erasure of memory cells M11.about.M22 can alternately be performed by applying a potential of about 18 V to substrate 10, with the word lines WL1 and WL2 grounded.
To program a specific memory cell M11, a high voltage of about 12 V is applied to the word line WL1 with the common source line CSL grounded, while a voltage of about 6 V are applied to bit line BL1. On the other hand, the word line WL2 and bit line BL2 are grounded, so as not to program the other three cells. Hot electrons generated at channel region 30 of memory cell M11 are then injected into its floating gate 22, thereby causing a threshold voltage of the memory cell M11 to become about 7 V.
To read out data stored in the memory cell M11, a voltage of about 1 V is applied to the bit line BL1, with common source line CSL grounded, and a voltage of about 5 V is applied to the word line WL1. If a memory cell M11 is programmed, its threshold voltage is about 7 V, and thus it functions as an off-transistor. On the other hand, if memory cell M11 is erased, then it functions as an on-transistor, with electrical current flowing on the bit line BL1. A sense amplifier (not shown) connected to the end of bit line BL1 detects the flowing electrical current, and thereby data stored in the memory cell M11 is accordingly determined.
As such, a memory cell, i.e. a floating gate transistor, normally functions like an enhancement mode transistor. However, a problem in the prior art is that a memory cell can have a negative threshold voltage, and thereby functions like a depletion mode transistor. A memory cell with such a negative threshold voltage after erasure is referred to as an over-erased memory cell. Such can be produced by variations or discrepancies in process and erase timing, or an increase of erase cycles. When the memory cell operates in depletion mode, it stays at a conductive state, even when not selected, and may prevent the cells on the same bit line from being read correctly. For example, suppose that the memory cell M22 is in the over-erased state. Then, when data is read-out from a selected one of other memory cells in the same column as the memory cell M22, error data may be read-out since the memory cell M22 is in a conductive state. Thus, a single over-erased memory cell can lead to failure of the entire memory.
A technique for solving the above-mentioned problem is to use an array of split-type flash EEPROM cells, as disclosed in U.S. Pat. No. 5,670,809. The array includes a plurality of n.sup.+ buried diffusion layers, i.e. drain/source regions, formed in a p-type semiconductor substrate to extend in parallel to one another in a column direction. Two neighboring ones of the diffusion layers define between them a plurality of channel regions spaced apart in the column direction and extending in the row direction. A plurality of floating gates are arranged in a matrix form of rows and columns so as to be placed over portions of the drain regions and the channel regions respectively interposing thick and thin insulating layers.
A plurality of control gate strips, i.e. word lines, extend in the row direction over the floating gates through an insulating layer, over the portion of the channel regions not covered by the floating gates through a split gate insulating layer, and over the source regions through a thick insulating layer. Thus, each of the split-type flash EEPROM cells has a structure in which a floating gate transistor and a split gate transistor are connected in series between drain and source regions.
Accordingly, even though a floating gate transistor could operate in a depletion mode due to over-erasure, there will still be no current flowing between the drain and source regions in a read-out operation. Thus is because the split gate transistor operates in an enhancement mode when the series-connected floating gate transistor is not selected, i.e. when 0 V is applied to its control gate. Thus, the split gate type cell eliminates the problem arising from over-erasure. However, the split gate arrangement requires a larger cell size, thereby limiting the number of flash EEPROM cells in a flash EEPROM cell array with a given area.